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cy7c65642 hx2vl ? very low power usb 2.0 tetrahub? controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-65659 rev. *e revised may 9, 2013 hx2vl ? very low power usb 2.0 tetrahub? controller features high-performance, low-power usb 2.0 hub, optimized for low-cost designs with minimum bill-of-material (bom). usb 2.0 hub controller ? compliant with usb2.0 specification ? up to four downstream ports support ? downstream ports are backward compatible with fs, ls ? multiple translator (tt), one per downstream port for maximum performance. very low-power consumption ? supports bus-powered and self-powered modes ? auto switching between bus-powered and self-powered ? single mcu with 2 k rom and 64 byte ram ? lowest power consumption. highly integrated solution for reduced bom cost ? internal regulator ? single power supply 5 v required. ? provision of connecting 3.3 v with external regulator. ? integrated upstream pull-up resistor ? integrated pull-down resistors for all downstream ports ? integrated upstream /downstream termination resistors ? integrated port status indicator control ? 12-mhz +/-500 ppm external crystal with drive level 600 ? w (integrated pll) clock i nput with optional 27/48-mhz oscillator clock input. ? internal power failure de tection for esd recovery downstream port management ? support individual and ganged mode power management ? overcurrent detection ? two status indicators per downstream port ? slew rate control for emi management maximum configurability ? vid and pid are configurab le through external eeprom ? number of ports, remov able/non-removable ports are configurable th rough eeprom and i/o pin configuration ? i/o pins can configure gang/individual mode power switching, reference clock source and polarity of power switch enable pin ? configuration options also available through mask rom available in space saving 48-pin tqfp (7 7 mm) and 28-pin qfn (5 5 mm) packages supports 0 ? c to +70 ? c temperature range d+ d- 3.3 v i/p (with ext. reg. & 28-qfn nc (with ext. reg. & 48-tqfp) 3.3 v o/p (for int. reg.) hub repeater routing logic usb downstream port 1 usb 2.0 phy port control usb downstream port 2 usb 2.0 phy port control usb downstream port 3 usb 2.0 phy port control usb downstream port 4 usb 2.0 phy port control mcu ram rom usb upstream port usb 2.0 phy pll d+ d- p w r # [1] o v r # [1] led d+ d- p w r # [2] o v r # [2] led d+ d- p w r # [3] o v r # [3] led d+ d- p w r # [4] o v r # [4] led i2c / spi 12/27/48 mhz osc-in or 12 mhz crystal transaction translator x 4 regulator serial interface engine hs usb control logic 3.3 v 5 v i/p (for internal regulator) nc (for external regulator) 1.8 v block diagram
cy7c65642 document number: 001-65659 rev. *e page 2 of 23 contents introduction ....................................................................... 3 hx2vl architecture .......................................................... 3 usb serial interface engine ... ..................................... 3 hs usb control logic ................................................. 3 hub repeater .............................................................. 3 mcu ............................................................................ 3 transaction translator ........... ..................................... 3 port control ................................................................. 3 applications ...................................................................... 3 functional overview ........................................................ 4 system initialization ..................................................... 4 enumeration ................................................................ 4 multiple transaction translato r support ..................... 4 upstream port ............................................................. 4 downstream ports ....................................................... 4 power switching .......................................................... 4 overcurrent detection ................................................. 4 port indicators ............................................................. 4 power regulator .... .............. .............. .............. ............ 5 external regulation scheme .. .............. .............. ......... 5 internal regulation scheme ........................................ 5 pin configurations ........................................................... 6 pin definitions .................................................................. 8 pin definitions ................................................................ 10 eeprom configuration options .............. .............. ....... 12 pin configuration options ............................................. 13 power on reset .................... ................................... 13 gang/individual power switching mode .................... 13 power switch enable pin polarity ............................. 13 port number configuration ........................................ 13 non removable ports configuration ......................... 13 reference clock configuration ................................. 13 absolute maximum ratings .......................................... 14 operating conditions ..................................................... 14 electrical characteristics ............................................... 15 dc electrical characteristics ..................................... 15 ac electrical characteristics ..................................... 16 thermal resistance ........................................................ 16 ordering information ...................................................... 17 ordering code definitions ..... .................................... 17 package diagrams .......................................................... 18 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 appendix: silicon erra ta for the hx2vl, cy7c65642 product family ....... .............. .............. ........ 21 part numbers affected .............................................. 21 hx2vl qualification status ....................................... 21 hx2vl errata summary ............................................ 21 document history page ................................................. 22 sales, solutions, and legal information ...................... 23 worldwide sales and design s upport ......... .............. 23 products .................................................................... 23 psoc solutions ......................................................... 23
cy7c65642 document number: 001-65659 rev. *e page 3 of 23 introduction hx2vl is cypress?s next generatio n family of high- performance, very low-power usb 2.0 hub cont rollers. hx2vl has integrated upstream and downstream transce ivers; a usb serial interface engine (sie); usb hub control and repeater logic; and transaction translator (tt) logic. cypress has also integrated external components such as voltage regulator and pull-up/pull-down resistors, reducing the overall bom required to implement a usb hub system. the cy7c65642 is a part of the hx2vl portfolio with four downstream ports and an independent tt dedicated for each downstream port. this device option is for low-power but high-performance applications that require up to four downstream ports. the cy7c65642 is available in 48-pin tqfp and 28-pin qfn package options. all device options are supported by cypress?s world class reference design kits, which include board schematics, bom, gerber files, orcad files, and thorough design documentation. hx2vl architecture the block diagram on page 1 shows the hx2vl tetrahub? architecture. usb serial interface engine the sie allows hx2vl to communicate with the usb host. the sie handles the following usb activities independently of the hub control block. bit stuffing and unstuffing checksum generation and checking token type identification address checking. hs usb control logic ?hub control? block co-ordinates enumeration, suspend and resume. it generates status and control signals for host access to the hub. it also includes the frame timer that synchronizes the hub to the host. it has status/c ontrol registers which function as the interface to the firmware in the mcu. hub repeater the hub repeater manages the connectivity between upstream and downstream facing ports t hat are operating at the same speed. it supports full and high-speed connectivity. according to the usb 2.0 specification, the hub repeater provides the following functions: sets up and tears down connectivity on packet boundaries ensures orderly entry into and out of ?suspend? state, including proper handling of remote wakeups. mcu the hx2vl has mcu with 2 k rom and 64 byte ram. the mcu operates with a 12 mhz clock to decode usb commands from host and respond to the host. it can also handle gpio settings to provide higher flexibility to the customers and control the read interface to the eeprom which has extended configuration options. transaction translator the tt translates data from one speed to another. a tt takes high-speed split transactions and translates them to full or low-speed transactions when the hub is operating at high-speed (the upstream port is connected to a high speed host controller) and has full or low- speed devices attached. the operating speed of a device attached on a downstream port determines whether the routing logic connects a port to the tt or to hub repeater. when the upstream host and do wnstream device are functioning at different speeds, the data is routed through the tt. in all other cases, the data is routed through the repeater. for example, if a full or low-speed device is c onnected to the high-speed host upstream through the hub, then the data transfer route includes tt. if a high-speed device is connected to the high-speed host upstream through the hub, the transfer route includes the repeater. when the hub is connected to a full-speed host controller upstream, then high-speed peripheral does not operate at its full capability. these devices only work at full speed. full and low-speed devices connected to this hub operate at their normal speed. port control the downstream ?port control? block handles the connect/disconnect and over current detection as well as the power enable and led control. it also generates the control signals for the downstream transceivers. applications typical applications for the hx2vl device family are: docking stations standalone hubs monitor hubs multi-function printers digital televisions advanced port replicators keyboard hubs gaming consoles
cy7c65642 document number: 001-65659 rev. *e page 4 of 23 functional overview the cypress cy7c65642 usb 2.0 hubs are low-power hub solutions for usb which provide maximum transfer efficiency with no tt multiplexing between downstream ports. the cy7c65642 usb 2.0 hubs integrate 1.5 k ? upstream pull-up resistors for full speed operation and all downstream 15 k ? pull-down resistors and series termination resistors on all upstream and downstream d+ and d? pins. this results in optimization of system costs by pr oviding built-in support for the usb 2.0 specification. system initialization on power up, cy7c65642 has an option to enumerate from the default settings in the mask rom or from reading an external eeprom for configuration informati on. at the most basic level, this eeprom has the vendor id (vid) and the product id (pid), for the customer's application. for more specialized applications, other configuration options can be specified. see eeprom configuration options on page 12 for more details. cy7c65642 verifies the checks um before loading the eeprom contents as the descriptors. enumeration cy7c65642 enables the pull-up resistor on d+ to indicate its presence to the upstream hub, after which a usb bus reset is expected. after a usb bus reset, cy7c65642 is in an unaddressed, unconfigured state (c onfiguration value set to?0?). during the enumeration process, the host sets the hub's address and configuration. after the hub is configured, the full hub functionality is available. multiple transaction translator support after tetrahub is configured in a high speed system, it is in single tt mode. the host may then set the hub into multiple tt mode by sending a setinterface command. in multiple tt mode, each full speed port is handled independently and thus has a full 12 mbps bandwidth available. in single tt mode, all traffic from the host destined for full or low- speed ports are forwarded to all of those ports. this means that the 12 mbps bandwidth is shared by all full and low-speed ports. upstream port the upstream port includes the tran smitter and the receiver state machine. the transmitter and receiver operate in high speed and full speed depending on the current hub configuration. the transmitter state machine monitors the upstream facing port while the hub repeater has connectivity in the upstream direction. this machine preven ts babble and disconnect events on the downstream facing ports of this hub from propagating and causing the hub to be disabled or disconnected by the hub to which it is attached. downstream ports the cy7c65642 supports a maximum of four downstream ports, each of which may be marked as usable or removable in the eeprom configuration, see eeprom configuration options on page 12 . additionally, it can also be configured by pin strapping, see pin configuration options on page 13 . downstream d+ and d? pull-down resistors are incorporated in cy7c65642 for each port. before the hubs are configured, the ports are driven single ended zero, ((se0) where both d+ and d? are driven low) and are set to the unpowered state. when the hub is configured, the ports ar e not driven and the host may power the ports by sending a setportpower command for each port. after a port is powered, any connect or disconnect event is detected by the hub. any change in the port state is reported by the hubs back to the host through the status change endpoint (endpoint 1). on receipt of setportreset request for a port with a device connected, the hub does as follows: performs a usb reset on the corresponding port puts the port in an enabled state enables babble detection after the port is enabled. babble consists of a non idle condition on the port after eof2. if babble is detected on an enabled port, that port is disabled. a clearportenable request from the host also disables the specified port. downstream ports can be individually suspended by the host with the setportsuspend request. if the hub is not suspended, a remote wakeup event on that port is reflected to the host through a port change indication in the hub status change endpoint. if the hub is suspended, a remote wakeup event on this port is forwarded to the host. the host may resume the port by sending a clearportsuspend command. power switching the cy7c65642 includes interface signals for external port power switches. both ganged and individual (per-port) configurations are supporte d by pin strapping, see pin configuration options on page 13 . after enumerating, the host may power each port by sending a setportpower request for that port. power switching and overcurrent detection are mana ged using respective control signals (pwr#[n] and ovr#[n]) which are connected to an external power switch device. both high/low enabled power switches are supported and the polarity is configured through gpio setting, see pin configuration options on page 13 . overcurrent detection the ovr#[n] pins of the cy7c65642 series are connected to the respective external power switch?s port overcurrent indication (output) signals. after detecting an overcurrent condition, hub reports overcurrent condition to the host and disables the pwr#[n] output to the external power device. ovr#[n] has a setup time of 20 ns. it takes 3 to 4 ms from overcurrent detection to deassertion of pwr#[n] port indicators the usb 2.0 port indicators are also supported directly by cy7c65642. according to the specification, each downstream port of the hub optionally suppor ts a status indicator. the presence of indicators for downst ream facing ports is specified by bit 7 of the whubcharacteristics field of the hub class descriptor. the default cy7c65642 descriptor specifies that the port indicators are supported. the cy7c65642 port indicators has two modes of operation: automatic and manual.
cy7c65642 document number: 001-65659 rev. *e page 5 of 23 on power up the cy7c65642 defaul ts to automatic mode, where the color of the port indicator (green, amber, off) indicates the functional status of the cy7c 65642 port. the leds are turned off when the device is suspended. note pin-strapping green#[1] and green#[2] enables proprietary function that may affect the normal functionality of hx2vl. configuring port #1 and #2 as non-removable by pin-strapping should be avoided power regulator cy7c65642 requires 3.3 v source power for normal operation of internal core logic and usb physical layer (phy). the integrated low-drop power regulator converts 5 v power input from usb cable (vbus) to 3.3 v source power. the 3.3 v power output is guaranteed by an internal voltage reference circuit when the input voltage is within the 4 v?5.5 v range. the regulator?s maximum current loading is 150 ma, which provides tolerance margin over cy7c65642?s normal power consumption of below 100 ma. the on chip regulator has a quiescent current of 28 a. external regulation scheme cy7c65642 supports both external regulation and internal regulation schemes. when an external regulation is chosen, then for the 48-pin package, vcc and vreg are to be left open with no connection. the external regulator output 3.3 v has to be connected to vcc_a and vcc_d pins. this connection has to be done externally, on board. for the 28-pin package, the 3.3 v output from the extern al regulator has to be connected to vreg, vcc_a and vcc_d. the v cc pin has to be left open with no connection. from the external input 3.3 v, 1.8 v is internally generated for the chip?s internal usage. internal regulation scheme when the built-in internal regulator is chosen, then the vcc pin has to be connected to a 5 v, in both 48-pin and 28-pin packages. internally, the built-in regulator generates a 3.3 v and 1.8 v for the chip?s internal usage. also a 3.3 v output is available at vreg pin, that has to be connected externally to vcc_a and vcc_d. port status indicator led vcc_d vcc external ? regulation ? scheme vcc_a vreg nc nc 5 ? v ? to ? 3.3 ? v ? regulator vcc_a vcc_d vreg vcc nc cy7c65642 48 ? pin cy7c65642 28 ? pin 5 ? v ? to ? 3.3 ? v ? regulator 3.3 ? v 3.3 ? v vcc_d vcc internal ? regulation ? scheme vcc_a vreg 5 ? v vcc_a vcc_d vreg vcc 5 ? v cy7c65642 48 ? pin cy7c65642 28 ? pin
cy7c65642 document number: 001-65659 rev. *e page 6 of 23 pin configurations figure 1. 48-pin tqfp (7 7 1.4 mm) pinout amber[2] / spi_mosi / pwr_pin_pol 36 green[2] / spi_miso / fixed_port2 35 vcc_d 34 amber[3] / set_port_num2 33 green[3] / fixed_port3 32 pwr#[3] 31 ovr#[3] 30 pwr#[4] 29 ovr#[4] 28 test / i2c_scl 27 sel48 25 vcc_a 1 gnd 2 d- 3 d+ 4 dd-[1] 5 vcc_a 7 gnd 8 dd-[2] 9 dd+[2] 10 rref 11 vcc_a 12 amber[4] / set_port_num1 24 green[4] / fixed_port 4 23 dd+[4] 22 dd-[4] 21 gnd 20 vcc_a 19 dd+[3] 18 dd-[3] 17 vcc_a 16 xout 15 xin 14 gnd 13 selfpwr 37 vcc_d 38 gang 39 ovr#[2] 40 pwr#[2] 41 ovr#[1] 42 pwr#[1] / i2c_sda 43 sel27 44 green[1] / spi_sk / fixed_port 1 45 amber[1] / spi_cs 46 vcc 47 vreg 48 reset# 26 5 dd+[1] cy7c65642 48-pin tqfp
cy7c65642 document number: 001-65659 rev. *e page 7 of 23 figure 2. 28-pin qfn (5 5 0.8 mm) pinout pin configurations (continued) d+ dd - [1] vcc a _ ovr # [3] 1 2 3 4 5 6 18 17 16 15 12 11 10 9 8 22 23 24 - xin rref selfpwr gang vcc vreg test/i2c_scl reset# 7 14 13 21 20 19 25 26 27 28 xout pwr#/ i2c_sda d- d d+ [1] d d+ [4] d d- [4] d d+ [2] d d- [2] d d+ [3] dd - [3] vcc a _ vcc a _ vc c d _ ovr # [4] ovr # [1] ov r # [2] 28-pin qfn cy7c65642
cy7c65642 document number: 001-65659 rev. *e page 8 of 23 pin definitions 48-pin tqfp package pin name pin no. type [1] description power and clock vcc_a 1 p v cc_a . 3.3 v analog power to the chip. vcc_a 7 p v cc_a . 3.3 v analog power to the chip. vcc_a 12 p v cc_a . 3.3 v analog power to the chip. vcc_a 16 p v cc_a . 3.3 v analog power to the chip. vcc_a 19 p v cc_a . 3.3 v analog power to the chip. vcc_d 34 p v cc_d . 3.3 v digital power to the chip. vcc_d 38 p v cc_d . 3.3 v digital power to the chip. vcc 47 p v cc . 5 v input to the internal regulator; nc if using external regulator vreg 48 p v reg . 5?3.3 v regulator o/p during internal regul ation; nc if using external regulator. gnd 2 p gnd . connect to ground with as short a path as possible. gnd 8 p gnd . connect to ground with as short a path as possible. gnd 13 p gnd . connect to ground with as short a path as possible. gnd 20 p gnd . connect to ground with as short a path as possible. xin 14 i 12-mhz crystal clock inpu t, or 12/27/48mhz clock input xout 15 o 12-mhz crystal out. (nc if external clock is used). sel48 / sel27 25 / 44 i clock source selection inputs . 00: reserved 01: 48-mhz osc-in 10: 27-mhz osc-in 11: 12-mhz crystal or osc-in reset# 26 i active low reset . external reset input, default pull high 10 k ? ; when reset = low, whole chip is reset to the initial state selfpwr 37 i self power . input for selecting self/bus power. 0 is bus powered, 1 is self powered. gang 39 i/o gang . default is input mode after power-on-reset. gang mode: input:1 -> output is 0 for normal operation and 1 for suspend individual mode: input:0 -> output is 1 for normal operation and 0 for suspend refer to gang / individual power switching modes in pin configuration options on page 13 for details. rref 11 i/o 649 ? resistor must be connected between rref and ground. system interface te s t i 2 c_scl 27 i(r dn ) i/o(r dn ) test . 0: normal operation and 1: chip will be put in test mode. i 2 c_scl . can be used as i 2 c clock pin to access i 2 c eeprom. upstream port d? 3 i/o/z upstream d? signal . d+ 4 i/o/z upstream d+ signal . note 1. pin types: i = input, o = output, p = power/ground, z = high impedance, r dn = pad internal pull down resistor, r up = pad internal pull up resistor.
cy7c65642 document number: 001-65659 rev. *e page 9 of 23 downstream port 1 dd?[1] 5 i/o/z downstream d? signal . dd+[1] 6 i/o/z downstream d+ signal . amber[1] spi_cs 46 o(r dn ) o(r dn ) led . driver output for amber led. port indicator support. spi_cs . can be used as chip select to access external spi eeprom. green[1] [2] spi_sk fixed_port1 45 o(r dn ) o(r dn ) i(r dn ) led . driver output for green led. port indicator support. spi_sk . can be used as spi clock to access external spi eeprom. fixed_port1 . at por used to set port1 as non removable port. refer pin configuration options on page 13 . ovr#[1] 42 i(r up ) overcurrent condition detection input . active low overcurrent condition detection input. pwr#[1] i 2 c_sda 43 o/z i/o power switch driver output . default is active low. i 2 c_sda . can be used as i 2 c data pin, connected with i 2 c eeprom. downstream port 2 dd?[2] 9 i/o/z downstream d? signal . dd+[2] 10 i/o/z downstream d+ signal . amber[2] spi_mosi pwr_pin_pol 36 o(r dn ) o(r dn ) i(r dn ) led . driver output for amber led. port indicator support. spi_mosi . can be used as data out to access external spi eeprom. pwr_pin_pol . used for power switch enable pin polarity setting. refer pin configuration options on page 13 . green[2] [2] spi_miso fixed_port2 35 o(r dn ) i(r dn ) i(r dn ) led. driver output for green led. port indicator support. spi_miso. can be used as data in to access external spi eeprom. fixed_port2. at por used to set port2 as non removable port. refer pin configuration options on page 13 . ovr#[2] 40 i(r up ) overcurrent condition detection input . active low overcurrent condition detection input. pwr#[2] 41 o/z power switch driver output . default is active low downstream port 3 dd?[3] 17 i/o/z downstream d? signal . dd+[3] 18 i/o/z downstream d+ signal . amber[3] set_port_num2 33 o(r dn ) i(r dn ) led . driver output for amber led. port indicator support. set_port_num2 . used to set port numbering along with set_port_num1. refer pin configuration options on page 13 . green[3] fixed_port3 32 o(r dn ) i(r dn ) led. driver output for green led. port indicator support. fixed_port3 . at por used to set port3 as non removable port. refer pin configuration options on page 13 . ovr#[3] 30 i(r up ) overcurrent condition detection input . active low overcurrent condition detection input. pwr#[3] 31 o/z power switch driver output . default is active low. pin definitions (continued) 48-pin tqfp package pin name pin no. type [1] description note 2. pin-strapping green[1] and green[2] enables proprietary function that may affect the normal functionality of hx2vl. configuri ng port #1 and #2 as non-removable by pin-strapping should be avoided.
cy7c65642 document number: 001-65659 rev. *e page 10 of 23 downstream port 4 dd?[4] 21 i/o/z downstream d? signal . dd+[4] 22 i/o/z downstream d+ signal . amber[4] set_port_num1 24 o(r dn ) i(r dn ) led . driver output for amber led. port indicator support. set_port_num1 . used to set port numbering along with set_port_num2. refer ?pin configuration options? on page 13 green[4] fixed_port4 23 o(r dn ) i(r dn ) led . driver output for green led. port indicator support. fixed_port4 . at por used to set port4 as non removable port. refer pin configuration options on page 13 . ovr#[4] 28 i(r up ) overcurrent condition detection input . active low overcurrent condition detection input. pwr#[4] 29 o/z power switch driver output . default is active low. pin definitions (continued) 48-pin tqfp package pin name pin no. type [1] description pin definitions 28-pin qfn package pin name pin no. type [3] description power and clock vcc_a 5 p v cc_a . 3.3 v analog power to the chip. vcc_a 9 p v cc_a . 3.3 v analog power to the chip. vcc_a 14 p v cc_a . 3.3 v analog power to the chip. vcc_d 21 p v cc_d . 3.3 v digital power to the chip. vcc 27 p v cc . 5 v input to the internal regulator; nc if using external regulator vreg 28 p v cc . 5?3.3 v regulator o/p during internal regulation; 3.3 v i/p if using external regulator. xin 10 i 12-mhz crystal clock in put, or 12-mhz clock input xout 11 o 12-mhz crystal out. (nc if external clock is used). reset# 17 i active low reset . external reset input, de fault pull high 10k ohm; when reset = low, whole chip is reset to the initial state selfpwr 22 i self power . input for selecting self/bus power. 0 is bus powered, 1 is self powered. gang 23 i/o gang default is input mode after power-on-reset. gang mode: input:1 -> output is 0 for normal operation and 1 for suspend individual mode: input:0 -> output is 1 for normal operation and 0 for suspend refer to gang / individual power switching modes in pin configuration options on page 13 for details. rref 8 i/o 649- ? resistor must be connected between rref and ground system interface te s t i2c_scl 18 o(r dn ) i/o(r dn ) test . 0: normal operation & 1: chip will be put in test mode i2c_scl . i 2 c clock pin. pwr# [4] i2c_sda 26 i/o power switch driver output . default is active low i2c_sda . i 2 c data pin. notes 3. pin types: i = input, o = output, p = power/ground, z = high impedance, r dn = pad internal pull down resistor, r up = pad internal pull up resistor. 4. pwr#/i2c_sda can be used as either pwr# or i2c_sda but not as both. if eeprom is connected then the pin will act as i2c_sda, it will not switch to pwr# mode (as it does in 48-pin tqfp package).
cy7c65642 document number: 001-65659 rev. *e page 11 of 23 upstream port d? 1 i/o/z upstream d? signal . d+ 2 i/o/z upstream d+ signal . downstream port 1 dd?[1] 3 i/o/z downstream d? signal . dd+[1] 4 i/o/z downstream d+ signal . ovr#[1] 25 i(r up ) overcurrent condition detection input. active low overcurrent condition detection input. downstream port 2 dd?[2] 6 i/o/z downstream d? signal . dd+[2] 7 i/o/z downstream d+ signal . ovr#[2] 24 i(r up ) overcurrent condition detection input . active low overcurrent condition detection input. downstream port 3 dd?[3] 12 i/o/z downstream d? signal . dd+[3] 13 i/o/z downstream d+ signal . ovr#[3] 20 i(r up ) overcurrent condition detection input . active low overcurrent condition detection input. downstream port 4 dd?[4] 15 i/o/z downstream d? signal . dd+[4] 16 i/o/z downstream d+ signal . ovr#[4] 19 i(r up ) overcurrent condition detection input . active low overcurrent condition detection input. gnd pad p ground pin for the chip . it is the solderable exposed pad beneath the chip. refer to the figure 4 on page 19 . pin definitions (continued) 28-pin qfn package pin name pin no. type [3] description
cy7c65642 document number: 001-65659 rev. *e page 12 of 23 eeprom configuration options systems using cy7c65642 have the option of using the default descriptors to configure the hub . otherwise, it must have an external eeprom for the device to have a unique vid, and pid. the cy7c65642 can communicate with an spi (microwire) eeprom like 93c46 or i 2 c eeprom like 24c02. example eeprom connections are shown as follows: note the 28-pin qfn package includes only support for i 2 c eeprom like atmel/24c02n_su27 d, microchip/4lc028 sn0509, seiko/s24cs02avh9. the 48-pin tqfp package includes both i 2 c and spi eeprom connectivity options. in this case, user can use either spi or i 2 c connectivity at a time for communicating to eeprom. th e 48-pin package supports atmel/at93c46dn-sh-t, in addition to the above mentioned families. hx2vl can only read from spi eeprom. so field programming of eeprom will be supported only for i 2 c eeprom. the default vid and pi d are 0x04b4 and 0x6572. cy7c65642 verifies the check sum after power on reset and if validated loads the configuration from the eeprom. to prevent this configuration from being ov erwritten, amber[1] is disabled when the spi eeprom is present. byte 0: vid (lsb) least significant byte of vendor id byte 1: vid (msb) most significant byte of vendor id byte2: pid (lsb) least significant byte of product id byte 3: pid (msb)] most significant byte of product id byte 4: chksum cy7c65642 will ignore the eeprom settings if chksum is not equal to vid_lsb + vid_ msb + pid_lsb + pid_msb +1 byte 5: reserved set to feh byte 6: removableports removableports[4:1] are the bits that indicate whether the device attached to the corresponding downstream port is removable (set to 0) or non-removable (set to 1). bit 1 corresponds to port 1, bit 2 to port 2 and so on. default value is 0 (removable). these bit values are reported appropriately in the hubdescriptor:deviceremovable field. bits 0,5,6,7 are set to 0. byte 7: port number port number indicates the number of downstream ports. the values must be 1 to 4. default value is 4. byte 8: maximum power this value is reported in the configuration descriptor: bmax-power field and is the cu rrent in 2 ma increments that is required from the upstream hubs. the allowed range is 00h (0ma) to fah(500ma). default value is 32h (100ma) byte 9?15: reserved set to ffh (except 11 which is feh) byte 16: vendor string length length of the vendor string byte 17 - 63: vendor string value of vendor string in ascii code. byte 64: product string length length of the product string byte 65- 111: product string value of product string in ascii code byte value 00h vid_lsb 01h vid_msb 02h pid_lsb 03h pid_msb 04h chksum 05h reserved - feh 06h removable ports 07h port number 08h maximum power 09h?0fh reserved ? ffh (except 0bh which is feh) cs di sk do gnd nc2 nc1 vcc amber[1] amber[2] green[1] green[2] vdd at93c46 a0 a2 a1 gnd sda scl wp vcc test at24c02 vdd pwr#[1] i2c eeprom connection spi eeprom connection 10h vendor string length 11h?3fh vendor string (ascii code) 40h product string length 41h?6fh product string (ascii code) 70 h serial number length 71h?80h serial number string byte value
cy7c65642 document number: 001-65659 rev. *e page 13 of 23 byte 112: serial number length length of the serial number byte 113 onwards: serial number string serial number string in ascii code. pin configuration options power on reset the power on reset can be triggered by external reset or internal circuitry. the internal reset is in itiated, when there is an unstable power event for silicon?s internal core power (3.3 v 10% ). the internal reset is released 2.7 s 1.2% after supply reaches power good voltage (2.5 v to 2.8 v) . the external reset pin, continuously senses the voltage level (5 v) on the upstream vbus as shown in the figure. in the event of usb plug/unplug or drop in voltage, the external reset is triggered. this reset trigger can be configured using the resistors r1 and r2. cypress recommends that the reset time applied in external reset circuit should be longer than that of the internal reset time. gang/individual power switching mode a single pin is used to set individual / gang mode as well as output the suspend flag. this is done to reduce the pin count. the individual or gang mode is decided within 20 s after power on reset. it has a setup time of 1ns. 50 to 60ms after reset, this pin is changed to output mode. cy7c65642 outputs the suspend flag, once it is globally suspended. pull-down resistor of greater than 100k is needed for individual mode and a pull-up resistor greater than 100k is needed for gang mode. figure below shows the suspend led indicator schematics. the polarity of led must be followed, otherwise the suspend current will be over the spec limitation (2.5 ma). power switch enable pin polarity the pin polarity is set active-high by pin-strapping the pwr_pin_pol pin to 1 and acti ve-low by pin-strapping the pwr_pin_pol pin to 0. thus, both kinds of power switches are supported. this feature is not supported in 28-pin qfn package. port number configuration in addition to the eeprom c onfiguration, as described above, configuring the hub for 2/3/4 ports is also supported using pin-strapping set_port_num1 and set_port_num2, as shown in following table.pin strapping option is not supported in the 28-pin qfn package. non removable ports configuration in embedded systems, downstream ports that are always connected inside the system, can be set as non-removable (always connected) ports, by pin-strapping the corresponding fixed_port# pins 1~4 to high, be fore power on reset. at por, if the pin is pull high, the corresponding port is set to non-removable. this is not supported in the 28-pin qfn package. reference clock configuration this hub can support, optional 27/48-mhz clock source. when on-board 27/48-mhz clock is pr esent, then using this feature, system integrator can further reduce the bom cost by eliminating the external crystal. this is available through gpio pin configuration shown below. this is not supported in the 28-pin qfn package. global reset# int. 3.3v power-good detection circuit input (usb phy reset) ext. vbus power-good detection circuit input (pin"reset#") vbus (external 5v) r1 r2 int ext pcb silicon 0 : individual mode 1: gang mode suspend out vdd (3.3v) suspend indicator vdd (3.3v) 100k 100k gang/suspend silicon pcb gang mode individual mode table 1. features supported in 48-pin and 28-pin packages supported features 48-pin 28-pin port number configuration yes no non-removable port configuration yes no reference clock configuration yes no power switch enable polarity yes no led indicator yes no set_port_num2 set_port_num1 # ports 1 1 1 (port 1) 1 0 2 (port 1/2) 0 1 3 (port 1/2/3) 0 0 4 (all ports) sel48 sel27 clock source 0 1 48-mhz osc-in 1 0 27-mhz osc-in 1 1 12-mhz x?tal/osc-in
cy7c65642 document number: 001-65659 rev. *e page 14 of 23 absolute maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?60 c to +100 c ambient temperature ..................................... 0 c to +70 c 5 v supply voltage to ground potential ........?0.5 v to +6.0 v 3.3 v supply voltage to ground potential .....?0.5 v to +3.6 v voltage at open drain input pins (ovr#1-4, selfpwr, reset#) .. ..............?0.5 v to +5.5 v 3.3 v input voltage for digital i/o ................?0.5 v to +3.6 v fosc (oscillator or crystal fr equency) ........ 12 mhz 0.05% operating conditions ambient temperature ..................................... 0 c to +70 c ambient max junction temperature .............. 0 c to +125 c 5 v supply voltage to ground potential ......4.75 v to +5.25 v 3.3 v supply voltage to ground potential .....3.15 v to +3.6 v input voltage for usb signal pins ..................0.5 v to +3.6 v voltage at open drain input pins ........... .......?0.5 v to +5.0 v thermal characteristics 48-pin tqfp ................... 78.7 c/w thermal characteristics 28-pin qfn ..................... 33.3 c/w
cy7c65642 document number: 001-65659 rev. *e page 15 of 23 electrical characteristics dc electrical characteristics parameter description conditions min typ max unit external regulator internal regulator p d power dissipation excluding usb signals ? ? 432 mw v ih input high voltage ? 2 ? ? v v il input low voltage ? ? ? 0.8 v i l input leakage current full speed / low speed (0 < v in < v cc ) ?10 ? +10 ? a high speed mode (0 < v in < v cc ) ?5 0 +5 ? a v oh output voltage high i oh = 8 ma 2.4 ? ? v v ol output low voltage i ol = 8 ma ? ? 0.4 v r dn pad internal pull-down resistor ? 81 103 181 k ? r up pad internal pull-up resistor ? 81 103 181 k ? c in input pin capacitance full speed / low speed mode ? ? 20 pf high speed mode 4 4.5 5 pf i susp suspend current ? ? 0.786 1.043 1.3 ma i cc supply current 4 active ports full speed host, full speed devices ? 88.7 103.9 105.4 ma high speed host, high speed devices ? 81.9 88.2 89.3 ma high speed host, full speed devices ? 88.2 101.2 102.3 ma 3 active ports full speed host, full speed devices ? 79.1 91.6 93 ma high speed host, high speed devices ? 72.9 78.5 78.6 ma high speed host, full speed devices ? 75.9 88.7 88.8 ma 2 active ports full speed host, full speed devices ? 68.1 78.4 78.6 ma high speed host, high speed devices ? 61.9 67.6 69.6 ma high speed host, full speed devices ? 64.9 75.4 76.1 ma 1 active ports full speed host, full speed devices ? 57.1 66.3 66.7 ma high speed host, high speed devices ? 51.9 57.6 59.3 ma high speed host, full speed devices ? 54.7 61.1 62.5 ma no active ports full speed host ? 42.8 48.9 50.3 ma high speed host ? 44.2 49.1 50.6 ma
cy7c65642 document number: 001-65659 rev. *e page 16 of 23 ac electrical characteristics usb transceiver is usb 2.0 certified in low, full and high speed modes. both the upstream usb transceiver and all fo ur downstream transceivers have passed the usb-if usb 2.0 electrical certification testing. the 48-pin tqfp package can support communication to eeprom using either i 2 c or spi. the 28-pin qfn package can support only i 2 c communication to eeprom. ac characteristics of these two interfaces to eeprom are summar ized in tables below: ac characteristics of spi eeprom interface parameter parameter min typ max units t css cs setup time 3.0 ? ? s t csh cs hold time 3.0 ? ? t skh sk high time 1.0 ? ? t skl sk low time 2.2 ? ? t dis di setup time 1.8 ? ? t dih di hold time 2.4 ? ? t pd1 output delay to ?1? ? ? 1.8 t pd0 output delay to ?0? ? ? 1.8 ac characteristics of i 2 c eeprom interface parameter parameter 1.8 v?5.5 v 2.5 v?5.5 v units min max min max f scl scl clock frequency 0.0 100 0.0 400 khz t low clock low period 4.7 ? 1.2 ? us t high clock high period 4.0 ? 0.6 ? us t su:sta start condition setup time 4.7 ? 0.6 ? us t su:sto stop condition setup time 4.7 ? 0.6 ? us t hd:sta start condition hold time 4.0 ? 0.6 ? us t hd:sto stop condition hold time 4.0 ? 0.6 ? us t su:dat data in setup time 200.0 ? 100.0 ? ns t hd:dat data in hold time 0 ? 0 ? ns t dh data out hold time 100 ? 50 ? ns t aa clock to output 0.1 4.5 0.1 ? us t wr write cycle time ? 10 ? 5 ns thermal resistance parameter description 48-pin tqfp package 28-pin qfn package unit ? ja thermal resistance (junction to ambient) 78.7 33.3 c/w ? jc thermal resistance (junction to case) 35.3 18.4 c/w
cy7c65642 document number: 001-65659 rev. *e page 17 of 23 ordering code definitions ordering information ordering code package type CY7C65642-48AXC 48-pin tqfp bulk CY7C65642-48AXCt 48-pin tqfp tape and reel cy7c65642-28ltxc 28-pin qfn bulk x = blank or t blank = tube; t = tape and reel temperature range: c = commercial pb-free package type: xx = a or lt a = tqfp; lt = qfn pin count: xx = 48 or 28 part identifier technology code: c = cmos marketing code company id: cy = cypress c 65642 a -x x cy xx 7 c
cy7c65642 document number: 001-65659 rev. *e page 18 of 23 package diagrams the cy7c65642 is available in following packages: figure 3. 48-pin tqfp (7 7 1.4 mm) a48 package outline, 51-85135 51-85135 *b
cy7c65642 document number: 001-65659 rev. *e page 19 of 23 figure 4. 28-pin qfn (5 5 0.8 mm), lt28a (3.5 3.5 e-pad), sawn package outline, 001-64621 package diagrams (continued) the cy7c65642 is available in following packages: side view top view bottom view see notes mla ** lt28a 001-64621 package outline, 28l qfn 5x5x0.8mm, lt28 10/06/10 0.05 0.025 see note 1 3. package weight: ~0.05gr 1. hatch area is solderable exposed pad notes: 2. based on ref jedec # mo-220 4. dimensions are in millimeters 3.5x3.5 epad, sawn bovs 10/06/10 001-64621 **
cy7c65642 document number: 001-65659 rev. *e page 20 of 23 acronyms document conventions units of measure acronym description ac alternating current ascii american standard code for information interchange eeprom electrically erasable programmable read only memory emi electromagnetic interference esd electrostatic discharge gpio general purpose input/output i/o input/output led light emitting diode lsb least significant bit msb most significant bit pcb printed circuit board pll phase-locked loop por power on reset psoc ? programmable system-on-chip? qfn quad flat no-leads ram random access memory rom read only memory sie serial interface engine tqfp thin quad flat pack tt transaction translator usb universal serial bus symbol unit of measure c degree celsius khz kilohertz k ? kilohm mhz megahertz ? a microampere ? s microsecond ? w microwatt ma milliampere mm millimeter ms millisecond mw milliwatt ns nanosecond ? ohm % percent pf picofarad ppm parts per million vvolt wwatt
cy7c65642 document number: 001-65659 rev. *e page 21 of 23 appendix: silicon errata for th e hx2vl, cy7c65642 product family this section describes the errata for the hx2vl, cy7c65642. the details include errata trigger conditions, scope of impact, ava ilable workarounds, and silicon revision applicability. contact your local cypress sales repr esentative, if you have any questions. part numbers affected hx2vl qualification status product status: sampling hx2vl errata summary this is the initial version of the hx2vl errata. as of now, there is no known issue with respect to the hx2vl. part number device characteristics cy7c65642 usb 2.0 multi tt hub
cy7c65642 document number: 001-65659 rev. *e page 22 of 23 document history page document title: cy7c65642, hx2vl ? very low power usb 2.0 tetrahub? controller document number: 001-65659 rev. ecn orig. of change submission date description of change ** 3176751 swak 02/18/2011 new data sheet. *a 3250883 swak / aasi 06/29/2011 updated functional overview (updated port indicators (added a note ?pin-strapping green#[1] and green#[2] enables proprietary function that may affect the normal functionality of hx2vl. configuring port #1 and #2 as non-removable by pin-strapping should be avoided.?). updated pin configurations (updated figure 1 (pin of the 48-pin tqfp package was named self_pwr. it is changed to selfpwr.)). updated pin definitions (updated description of xin pin to ?12-mhz crystal clock input, or 12-mhz clock input? (since 28-pin package does not support 27 and 48 mhz), updated description of xo ut pin to ?12-mhz crystal out. (nc if external clock is used)?, changed value from 680 ? to 650 ?? in description of ? rref pin, changed description of ovr# pins from ?default is active low? to ?active low overcurrent condition detection input? (since the polarity is not configurable), changed all seven occu rrences of ?refer ?48-pin tqfp pin configuration? on page 5? to ?refer pin configuration options on page 13 ?, added note 2 and referred the same note in green#[1] and green#[2] pins). updated pin definitions (updated description of xin pin to ?12-mhz crystal clock input, or 12-mhz clock input? (since 28-pin package does not support 27 and 48 mhz), updated description of xo ut pin to ?12-mhz crystal out. (nc if external clock is used)?, changed descr iption of ovr# pins from ?default is active low? to ?active low overcurrent condition detection input? (since the polarity is not configurable)). updated functional overview (updated power regulator (changed regulator?s maximum current loadi ng from 200 ma to 150 ma)). updated pin configuration options (updated power switch enable pin polarity (replaced first two occurrences of th e word ?setting? with ?pin-strapping?)). updated electrical characteristics (updated dc electrical characteristics (updated maximum value of i susp parameter to 903 a, updated maximum values of i cc parameter)). *b 3327505 aasi 07/27/ 2011 changed status from preliminary to final. updated pin definitions (minor edits). updated ordering information (updated part numbers) and ordering code definitions . *c 3525169 aasi 02/16/2012 updated pin configurations (updated figure 1 (renamed spi_di to spi_mosi, renamed spi_do to spi_miso respectively for clarity)). updated pin definitions (renamed spi_di to spi_mosi, renamed spi_do to spi_miso respectively for clarity). updated pin definitions (updated description of pwr# of 28-pin package (to describe the alternate function i2c_sda)). *d 3637477 aasi 07/02/2012 updated eeprom configuration options (changed the value of byte 5 to feh to match with the tabular column). updated electrical characteristics (updated dc electrical characteristics (splitted the max column into two co lumns namely external regulator and internal regulator for i susp and i cc parameters and updated the corresponding values)). added thermal resistance . updated ordering information (updated part numbers). updated in new template. *e 3995708 prji 05/09/2013 added appendix: silicon errata for the hx2vl, cy7c65642 product family .
document number: 001-65659 rev. *e revised may 9, 2013 page 23 of 23 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c65642 ? cypress semiconductor corporation, 2011-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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